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HV256 32-Channel High Voltage Amplifier Array
Features
32 independent high voltage amplifiers 300V operating voltage 295V output voltage 2.2V/s typical output slew rate Adjustable output current source limit Adjustable output current sink limit Internal closed loop gain of 72V/V 12M feedback impedance Layout ideal for die applications
General Description
The Supertex HV256 is a 32-channel high voltage amplifier array integrated circuit. It operates on a single high voltage supply, up to 300V, and two low voltage supplies, VDD and VNN. The input voltage range is from 0V to 4.096V. The internal closed loop gain is 72V/V, giving an output voltage of 295V when 4.096V is applied. Input voltages of up to 5V can be applied, but will cause the output to saturate. The maximum output voltage swing is 5V below the VPP high voltage supply. The outputs can drive capacitive loads of up to 3000pF. The maximum output source and sink current can be adjusted by using two external resistors. An external RSOURCE resistor controls the maximum sourcing current and an external RSINK resistor controls the maximum sinking current. The current limit is approximately 12.5V divided by the external resistor value. The setting is common for all 32 outputs. A low voltage silicon junction diode is made available to help monitor the die temperature.
Applications
MEMS (microelectromechanical systems) driver Piezoelectric transducer driver Optical crosspoint switches (using MEMS technology)
Typical Application Circuit
Micro Processor
DAC DAC DAC DAC
Supertex HV256
VIN0 VIN1 VIN2 VIN3
VDD
VPP HVOUT0 HVOUT1 HVOUT2
x y y x
High Voltage Op-Amp Array
HVOUT3
MEMS Array HVOUT30 HVOUT31
DAC DAC
VIN30 VIN31
RSOURCE RSINK AGND VNN
HV256
Device HV256
-G indicates package is RoHS compliant (`Green')
Package Option 100-Lead MQFP HV256FG HV256FG-G
Absolute Maximum Ratings
Parameter VPP, High voltage supply AVDD, Analog low voltage positive supply DVDD, Digital low voltage positive supply AVNN, Analog low voltage negative supply DVNN, Digital low voltage negative supply Logic input voltage VSIG, Analog input signal SRVPP, VPP ramp up/down Storage temperature range Maximum junction temperature Value 310V 8.0V 8.0V -7.0V -7.0V -0.5V to DVDD 0V to 6.0V TBDV/usec -65C to 150C 150C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.
Operating Conditions
Symbol VPP VDD VNN IPP IDD INN TJ Parameter High voltage positive supply Low voltage positive supply Low voltage negative supply VPP supply current VDD supply current VNN supply current Operating temperature range Min 125 6.0 -4.5 -6.0 -10 Typ Max 300 7.5 -6.5 0.8 5.0 85 Units V V V mA mA mA C Conditions ------VPP = 300V, All HVOUT = 0V No load VDD = 6.0V to 7.5V VNN = -4.5V to -6.5V ---
Electrical Characteristics (over operating conditions, unless otherwise specified)
High Voltage Amplifier
Symbol HVOUT VIN VINOS SR BW AO AV RFB CLOAD ISOURCE ISINK RSOURCE RSINK CTDC PSRR Parameter HVOUT voltage swing Input voltage range Input voltage offset HVOUT slew rate rise HVOUT slew rate fall HVOUT -3dB channel bandwidth Open loop gain Closed loop gain Feedback resistance from HVOUT to ground HVOUTt capacitive load HVOUT sourcing current limiting range HVOUT sinking current limiting range External resistance range for setting maximum current source External resistance range for setting maximum current sink DC channel to channel crosstalk Power supply rejection ratio for VPP, VDD, VNN Min 0 0 70 68.4 9.6 0 385 385 25 25 -80 -40 Typ 2.2 2.0 4.0 100 72 12 550 550 Max VPP- 5.0 5.0 50 75.6 3000 715 715 250 250 Units V V mV V/s V/s KHz dB V/V M pF A A K K dB dB Conditions ----Input referred No Load No Load VPP = 300V --------RSOURCE = 25K RSINK = 25K ---------
2
HV256
Temperature Diode
Symbol PIV VF IF TC Parameter Peak inverse voltage Forward diode drop Forward diode current VF temperature coefficient Min Typ 0.6 -2.2 Max 5.0 100 Units V V A mV/C Conditions cathode to anode IF = 100A, anode to cathode at TA = 25C anode to cathode anode to cathode
HV256 Block Diagram
BYP-VPP BYP-VDD BYP-VNN To internal VPP bus To internal VDD bus To internal VNN bus Output Current Source Limiting for all HVOUT Output Current Sink Limiting for all HVOUT
RSOURCE
RSINK VPP VDD
VDD VPP
VDD VPP
GND VNN Anode Cathode
+
VIN31
+
VIN1
+
HVOUT0
VIN0
VNN
71R R
HVOUT1 VNN 71R R
3
HVOUT31 71R R
HV256
Power Up/Down Issues
External Diode Protection
The device can be damaged due to improper power up / down sequence. To prevent damage, please follow the acceptable power up / down sequences, and add two external diodes as shown in the diagram on the right. The first diode is a high voltage diode across VPP and VDD , where the anode of the diode is connected to VDD and the cathode of the diode is connected to VPP. Any low current, high voltage diode, such as a 1N4004, will be adequate. The second diode is a Schottky diode across VNN and DGND , where the anode of the Schottky diode is connected to VNN , and the cathode is connected to DGND. Any low current Schottky diode such as a 1N5817 will be adequate.
External Diode Protection Connection VDD
1N4004 or similar
VPP
VNN
1N5817 or similar
DGND
Suggested Power Up/Down Sequence
The HV256 needs all power supplies to be fully up and all channels refreshed with VSIG = 0V to force all high voltage outputs to 0V. Before that time, the high voltage outputs may have temporary voltage excursions above or below GND level depending on selected power up sequence. To minimize the excursions: 1. The VDD and VNN power supplies should be applied at the same time (or within a few nanoseconds). Suggested VPP ramp up speed should be 10msec or longer and ramp down to be 1msec or longer.
Acceptable Power Up Sequences
The HV256 can be powered up with any of the following sequences listed below. 1) VPP 2) VNN 3) VDD 4) Inputs and Anode 1) VNN 2) VDD 3) VPP 4) Inputs and Anode 1) VDD & VNN 2) Inputs 3) VPP 4) Anode
Acceptable Power Down Sequences
The HV256 can be powered down with any of the following sequences listed below. 1) Inputs and Anode 2) VDD 3) VNN 4) VPP 1) Inputs and Anode 2) VPP 3) VDD 4) VNN 1) Anode 2) VPP 3) Inputs 4) VNN & VDD
Recommended Power Up/Down Timing
300V
VPP VDD VNN VIN HVOUT
Gnd +/- V offset X 72
0V
6.5V 0V 0V -5.5V
0V 0V
HVOUT Level at Power UP
VPP VDD VNN
Power Up Sequence
VDD Before VNN
0V
VNN Before VDD
VPP VDD VNN
0V
6.5V 0V
6.5V 0V
0V -5.5V
0V -5.5V
HVOUT
0V -5.5V
HVOUT
6.5V 0V
4
HV256
RSINK / RSOURCE
The VDD_BYP ,VDD_BYP ,and VNN_BYP pins are internal. high impedance current. mirror gate nodes, brought out to mantain stable opamp biasing currents in noisy power supply environments. 0.1uF/25V bypass capacitors, added from VPP_BYP pin to VPP , from VDD_BYP pin to VDD , and from VNN_BYP to VNN,will force the high impedance gate
VPP BYP _VPP Cap 0.1uF / 25V BYP _VPP BYP _VDD BYP _VDD Cap 0.1uF / 25V VDD BYP _VNN BYP _VNN Cap 0.1uF / 25V VNN Current limit Set by RSINK Current limit
nodes to follow fluctuation of power lines. The expected voltages at the VDD_BYP, and VNN_BYP pins are typically 1.5 volts from their respectful power supply. The expected voltage at VPP_BYP is typically 3V below VPP.
Set by RSOURCE To internal biasing HVOUT0 HVOUT31 HVOpamp
HVOpamp
Typical Characteristics
ISINK vs RSINK
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC) 600
ISOURCE vs RSOURCE
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC) 600
500
500
400
ISOURCE (A)
400
300
ISINK (A)
300
200
200
100
max min
max
100
min
0 25k 150k 250k
0
25k
150k
250k
RSOURCE (K)
RSINK (K)
5
HV256
Typical Characteristics (cont.)
VNN PSSR vs Frequency
Temperature Diode vs Temperature
(VPP = 300V, VDD = 6.5V, VNN = 5.5V)
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC) -50 -40
700
-10 C
O
VNN PSSR (dB)
-30 -20 -10 0 10 100 1k 10k 100k 1M
max 600 max min 500 max min 400 85OC min 25 C
O
Vf (mV)
Frequency
300 1A 20A 40A 60A 80A 100A
Input Offset vs VIN and Temperature
(VPP = 300V, VDD = 6.5V, VNN = 5.5V )
3.5 3.0 2.5 2.0
Diode Biasing Current (A)
VPP PSSR vs Frequency
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC) -50 -40
HVOUT (mV)
VPP PSSR (dB)
1.5
-30 -20 -10 0 10 100 1k 10k 100k 1M
Offset at -10OC Offset at 25OC Offset at 85OC
-2.0 -2.5 -3.0 -3.5 -4.0 -4.5 1 2 3
Frequency (Hz)
VDD PSSR vs Frequency
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC) -50 -40
73.97 73.96
VIN (Volts)
Gain vs VIN
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = -10O, +25O, +85OC )
VDD PSSR (dB)
-30
73.95
HVOUT (V)
10 100 1k 10 100 1M
73.94 73.93 72.74 72.73 72.72 72.71 72.70 72.69
1 2 3
-20 -10 0
Frequency (Hz)
VIN (Volts)
6
HV256
Pad Configuration (not drawn to scale)
Do Not Bond. Leave Floating.
Byp-VNN Byp-VDD
Do Not Bond. For testing only. Anode Cathode RSINK RSOURCE Byp-VPP VPP HVOUT31 HVOUT30 HVOUT29 HVOUT28 HVOUT27 HVOUT26 HVOUT25 HVOUT24 HVOUT23 HVOUT22 HVOUT21 HVOUT20 HVOUT19 HVOUT18 HVOUT17 HVOUT16 HVOUT15 HVOUT14 HVOUT13 HVOUT12 HVOUT11 HVOUT10 HVOUT 9 HVOUT 8 HVOUT 7 HVOUT 6 HVOUT 5 HVOUT 4 HVOUT 3 HVOUT 2 HVOUT 1 HVOUT 0 VPP
GND
GND
VNN VNN GND
VDD VDD
VNN
VDD VNN
Do Not Bond. Leave Floating.
VIN31 VIN30 VIN29 VIN28 VIN27 VIN26 VIN25 VIN24 VIN23 VIN22 VIN21 VIN20 VIN19 VIN18 VIN17 VIN16 VIN15
VIN14 VIN13 VIN12 VIN11 VIN10 VIN9 VIN8 VIN7 VIN6 VIN5 VIN4 VIN3 VIN2 VIN1 VIN0
GND
VDD
7
HV256
Pad Coordinates
Chip size: 17160m x 5830m Center of die is (0,0)
Pad Nam e V PP HVOUT0 HVOUT1 HVOUT2 HVOUT3 HVOUT4 HVOUT5 HVOUT6 HVOUT7 HVOUT8 HVOUT9 HVOUT10 HVOUT11 HVOUT12 HVOUT13 HVOUT14 HVOUT15 HVOUT16 HVOUT17 HVOUT18 HVOUT19 HVOUT20 HVOUT21 HVOUT22 HVOUT23 HVOUT24 HVOUT25 HVOUT26 HVOUT27
X (m ) -8338.5 -7895.0 -7448.5 -7001.5 -6554.5 -6107.5 -5660.5 -5213.5 -4766.5 -4319.5 -3872.5 -3425.5 -2978.5 -2531.5 -2084.5 -1637.5 -1190.5 -743.5 -296.5 150.0 597.5 1044.5 1491.5 1938.5 2385.5 2832.5 3279.5 3726.5 4173.5
Y( m ) 2708.5 2305.5 2305.5 2305.5 2305.5 2305.5 2305.5 2305.5 2305.5 2305.5 2305.5 2305.5 2305.5 2305.5 2305.5 2305.5 2305.5 2305.5 2305.5 2305.5 2305.5 2305.5 2305.5 2305.5 2305.5 2305.5 2305.5 2305.5 2305.5
Pad Name HVOUT28 HVOUT29 HVOUT30 HVOUT31 VPP Byp-VPP RSOURCE RSINK Cathode Anode VNN Byp-VDD Byp-VNN VDD GND VNN VDD GND VIN31 VIN30 VIN29 VIN28 VIN27 VIN26 VIN25 VIN24 VIN23 VIN22 VIN21
X( m) 4620.5 5067.5 5514.5 5961.5 6659 7045 7489 7969 8366 8366 8047 8047 8047 8047 8047 8066.5 8066.5 7867.0 5043.5 4638.5 4233.5 3828.5 3423.5 3018.5 2613.5 2208.5 1803.5 1398.5 993.5
Y( m) 2305.5 2305.5 2305.5 2305.5 2709 2709 2709 2709 2709 2199 425.0 125.5 -345.5 -704.5 -1424.0 -1590.0 -1958.5 -2192.0 -2686.0 -2686.0 -2686.0 -2686.0 -2686.0 -2686.0 -2686.0 -2686.0 -2686.0 -2686.0 -2686.0
Pa d Name VIN20 VIN19 VIN18 VIN17 VIN16 VIN15 VIN14 VIN13 VIN12 VIN11 VIN10 VIN9 VIN8 VIN7 VIN6 VIN5 VIN4 VIN3 VIN2 VIN1 VIN0 VDD VNN GND VDD VNN GND
X( m) 588.5 183.5 -221.5 -626.5 -1031.5 -1436.5 -2412.0 -2817 -3222 -3627 -4032 -4437 -4842 -5247 -5652 -6052 -6462 -6867 -7272 -7677 -8082 -8373 -8373 -8367 -8387 -8338.5 -8341.0
Y(m) -2686.0 -2686.0 -2686.0 -2686.0 -2686.0 -2686.0 -2686.0 -2686.0 -2686.0 -2686.0 -2686.0 -2686.0 -2686.0 -2686.0 -2686.0 -2686.0 -2686.0 -2686.0 -2686.0 -2686.0 -2686.0 -2250.5 -1949.0 -1561. -1143.0 577.5 916.5
8
HV256
Pin Description
Pin # 33, 100 99 42, 45, 87, 91 93 40, 44, 88, 94 92 39, 43, 86, 89 98 Function VPP BYP-VPP VDD BYP-VDD VNN BYP-VNN GND RSOURCE RSINK Anode Cathode VIN0 to VIN31 HVOUT0 to HVOUT31 Description High voltage positive supply. There are two pads. A low voltage 1.0 to 10nF decoupling decoupling capacitor across VPP and BYP-VPP is required. Analog low voltage positive supply. There are four pads. A low voltage 1.0 to 10nF decoupling decoupling capacitor across VDD and BYP-VDD is required. Analog low voltage negative supply. There are four pads. A low voltage 1.0 to 10nF decoupling decoupling capacitor across VNN and BYP-VNN is required. Digital ground. There are four pads. External resistor from RSOURCE to VNN sets output current sourcing limit. Current limit is approximately 12.5V divided by RSOURCE resistor value. External resistor from RSINK to VNN sets output current sinking limit. Current limit is approximately 12.5V divided by RSINK resistor value. Anode side of of a low voltage silicon diode that can be used to monitor die temperature. Cathode side of of a low voltage silicon diode that can be used to monitor die temperature. Amplifier inputs. Amplifier outputs.
97 95 96 48-79 1-32
9
HV256
Pin Configuration
80 81 51 50
100 1 30
31
100-Lead MQFP
(top view)
Pin Configuration
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Function HVOUT31 HVOUT30 HVOUT29 HVOUT28 HVOUT27 HVOUT26 HVOUT25 HVOUT24 HVOUT23 HVOUT22 HVOUT21 HVOUT20 HVOUT19 HVOUT18 HVOUT17 HVOUT16 HVOUT15 HVOUT14 HVOUT13 HVOUT12 HVOUT11 HVOUT10 HVOUT9 HVOUT8 HVOUT7 Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Function HVOUT6 HVOUT5 HVOUT4 HVOUT3 HVOUT2 HVOUT1 HVOUT0 VPP NC NC NC NC NC GND VNN NC VDD GND VNN VDD NC NC VIN0 VIN1 VIN2 Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Function VIN3 VIN4 VIN5 VIN6 VIN7 VIN8 VIN9 VIN10 VIN11 VIN12 VIN13 VIN14 VIN15 VIN16 VIN17 VIN18 VIN19 VIN20 VIN21 VIN22 VIN23 VIN24 VIN25 VIN26 VIN27 Pin 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Function VIN28 VIN29 VIN30 VIN31 NC NC NC NC NC NC GND VDD VNN GND NC VDD BYP-VNN BYP-VDD VNN Anode Cathode RSINK RSOURCE BYP-VPP VPP
Note: NC = No Connect 10
HV256
100-Lead MQFP Package Outline (FG)
20x14mm body, 3.15mm height (max.), 0.65mm pitch, 3.2mm footprint
D D1
E
Note 1 (Index Area E1/4 x D1/4)
1
E1
L2
100
Gauge Plane Seating Plane
L L1
1
e
b
Top View View B
A A2 A1
Seating Plane
View B
Side View
Note 1: A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.
Symbol MIN Dimension (mm) NOM MAX
Drawings not to scale.
A 2.50 3.15
A1 0.00 0.25
A2 2.50 2.70 2.90
b 0.22 0.40
D 22.95 23.20 23.45
D1 19.80 20.00 20.20
E 16.95 17.20 17.45
E1 13.90 14.00 14.20
e 0.65 BSC
L 0.73 0.88 1.03
L1 1.60 REF
L2 0.25 BSC
0O 7
O
1 5O 16O
JEDEC Registration MS-022, Variation GC-2, Issue B, Dec. 1996.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV256 B120406
11

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